RISC and CISC represent key processor architectures developed to boost CPU performance.
- RISC and CISC are popular processor architectures that utilize different data processing instruction sets to perform basic logical and input/output operations.Â
- This article explains the RISC and CISC processor architectures in detail, along with the key comparisons between them.
RISC (reduced instruction set computer) and CISC (complex instruction set computer) refer to the popular processor architectures that utilize different data processing instruction sets to perform basic logical and input/output operations. Each architecture has its own set of pros and cons.
Before we jump into the processor architectures, let’s first understand the workflow of a typical processor.
Processors or microcontrollers use â€˜instruction sets’ to carry out various tasks. Let’s consider an analogy. Say you train your pet to understand certain commands such as â€˜sleep’ and â€˜run,’ which are associated with specific tasks of sleeping and running. Later, when you throw a toy and give the instruction â€˜run’ to your pet, it runs and fetches the toy for you.
A typical central processing unit (CPU), the brain of a computer, works in a similar manner, wherein the CPU equates to processors and microcontrollers. Similar to the above example, we give instructions to the CPU, which triggers transistors to turn ON and OFF to perform specified instructions.
We input instructions in operation codes or opcodes, which are expressed in the form of 0s and 1s. Since it is difficult for humans to memorize and use combinations of 0s and 1s, we use human-understandable instructions. These instructions are represented via an assembly language, which is further converted into machine-understandable opcodes of 0s and 1s by compilers.
The collection of all such instructions forms an â€˜instruction set.’ This is an important component of any computing system as the design of several high-level languages such as Python, C#, and others depend on it. Moreover, the design of hardware and instruction sets is used as a metric to evaluate a CPU’s computational speed and performance.
A CPU’s performance is deduced based on the number of programs it can run in a given time span. Mathematically, this is represented as:
CPU performance =Time/Program = Instructions/Program X Cycles/Instructions X Time/Cycle â€¦.. [Equation 1]
As per this equation, CPU performance depends on the number of instructions in a computer program. This implies that the more instructions, the more time is needed to execute them. It can further be simplified into the number of clock cycles per instruction and time per cycle.
Thus, the CPU performance can be optimized in either of two ways:
- Reduce the number of instructions per program, or
- Minimize cycles per instruction.
Since these two options are complementary, achieving both at once is impossible. This means that improving one parameter may easily sacrifice the other. However, all this is just at the surface level; the real optimizations that we intend to introduce are deeply ingrained in the hardware and instruction set of the CPU.
The primary objective of RISC and CISC architectures is to improve CPU performance. The fundamental difference between the two is that RISC has less number of instructions, with each one capable of performing a single operation, while CISC has a large number of complex instructions capable of carrying out multiple internal operations.
The CPU industry includes companies supporting and backing either of the two architectures. For example, Intel’s machines use CPUs that run on the CISC architecture, while Apple’s CPUs and ARM’s machines come with RISC-based processors and microcontrollers.
CISC stands for â€˜Complex Instruction Set Computer.’ This architecture was introduced in the 1970s by Intel Corporation when the earliest computers focused on enhancing CPU speed by minimizing the number of instructions per program (as per equation 1). This objective was achieved by combining multiple simple commands into one complex instruction.
In the pet analogy, the command â€˜run’ can be referred to as a CISC instruction. When you instruct your pet to run, it performs a set of instructions such as â€˜track the toy,’ then â€˜pick the toy up,’ followed by â€˜get back to the owner,’ and finally, â€˜hand over the toy to the owner.’ As the example reveals, it is a lot more convenient and faster to give a single â€˜run’ instruction to your pet rather than giving it four independent commands. This is exactly why tech companies such as Intel preferred designing CISC processors in the initial computing years.
Let’s understand this with a simple CISC ADD instruction, which requires two inputs:
- Memory locations of two numbers essential for an addition
- Perform addition and store the result in the first memory location
| ADD 1800, 1801
The ADD instruction picks up numbers from memory locations 1800 and 1801 or registers. Later, the picked-up numbers are added and eventually stored in location 1800.
Here, a single ADD instruction performs multiple low-level operations, such as loading numbers from memory, performing the arithmetic ADD operation, and then storing the result in another memory. The compiler’s workload is reduced significantly here as high-level instructions are easily computed and stored. Moreover, these instructions consume minimum RAM as the hardware takes care of most tasks while decoding the instructions in the beginning stages.
Hence, in CISC architectures, the CPU is entitled to put in more work to perform a single instruction. As the execution of the instruction takes more time, clock speeds are compromised. Moreover, CISC operations require more transistors to decode complex instructions.
Commonly known examples of CISC processors are AMD, Intel x86, VAX, and System/360.
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RISC stands for â€˜Reduced Instruction Set Computer.’ These were introduced in the 1980s by David Patterson and John Hennessy to overcome the complexities of CISC processors. RISC processors work with more instructions; however, the number of cycles an instruction may take to execute is minimized. In general terms, a RISC machine takes one CPU cycle to complete one instruction. This may equate to the â€˜sleep’ instruction you gave your trained pet.
Let’s consider the same ADD instruction and look at how RISC devices accomplish it. To begin with, RISC machines do not execute the ADD instruction in one step. Instead, it is broken down into multiple steps. For example, you need to load the numbers from memory through a LOAD instruction, followed by an ADD instruction that adds them, and finally, a STORE instruction that stores the result in memory.
| Load X, 1600
| Load Y, 1601
| ADD X, Y
| Store 1600, X
In this example, the â€˜Load’ instruction loads data at memory location 1600 into register X. Similarly, the second â€˜Load’ instruction picks up data from 1601 and loads it into register Y. Later, the values in registers X and Y are added. Lastly, the result X of addition is stored at memory location 1600 or any other location. It is worth noting that operations in RISC-type processors are performed on â€˜registers’ rather than directly on memory.
Although the process seems intricate, as each of these instructions consumes only one clock cycle, the entire addition operation is accomplished in much fewer clock cycles. However, such time benefits also present some disadvantages. For instance, since RISC processors use simpler instruction sets, complex and high-level instructions need to be divided into multiple, simple instructions.
The task of breaking down complex commands into simpler ones is trivial and is accomplished by compilers. As a result, software components have more work to do in RISC than the processor’s hardware, as seen in CISC. This puts an additional responsibility on software designers as they are held accountable in case of compiler dysfunction.
Unlike CISC processors, the logic of RISC machines is simple to decode. Consequently, fewer transistors are required to complete tasks. RISC architecture uses a simplified set of instructions that tend to work less but execute at a significant pace. The key feature of such machines is that they enable developers to fit in more general registers in CPUs and thereby focus on employing parallel threads to complete complex yet optimized instructions. It boosts internal parallelism and speeds up the CPU’s instruction execution time.
ARM (Advanced RISC Machine) is a well-known example of the RISC framework. It is an architecture developed by Arm Ltd. that is based on the design principles of RISC. Its processors are observed in desktops, laptops, smartphones, gaming consoles, and several other smart IoT devices that are battery-operated where energy efficiency is essential.
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The CISC architecture tries to elevate CPU performance by finishing a task in minimal lines of assembly code, while RISC relies on the strategy of lowering the execution time of each instruction. For example, on an Intel 8086 processor (CISC device), multiple operations on two 8-bit numbers may require around 70 to 77 clock cycles. In contrast, a PIC microcontroller (RISC device) may take up to 38 clock cycles. As the example reveals, the RISC device is 2x faster than its CISC counterpart.
Since CISC devices take more time to execute a single operation, the architecture does not support the parallel processing and pipelining of instructions. On the contrary, in the RISC architecture, every instruction is completed in one clock cycle, thereby promoting the pipelining of instructions.
Here are some of the key differences between CISC and RISC processor architectures:
|1.Â Â Â||CISC is the short form for Complex Instruction Set Computer.||RISC refers to Reduced Instruction Set Computer.|
|2.Â Â Â||The CSIC architecture processes complex instructions that require several clock cycles for execution. On average, it takes two to five clock cycles per instruction (CPI).||The RISC architecture executes simple yet optimized instructions in a single clock cycle. It processes instructions at an average speed of 1.5 clock cycles per instruction (CPI).|
|3.Â Â Â||CISC focuses on hardware, such as transistors, to execute instructions.||RISC focuses more on software such as codes or compilers to execute instructions.|
|4.Â Â Â||Implementation of complex instructions is enabled through memory units.||RISC lacks special memory and thus utilizes specialized hardware to execute instructions.|
|5.Â Â Â||CISC devices are installed with a microprogramming unit.||RISC devices are embedded with a hardwired programming unit.|
|6.Â Â Â||CISC uses a variety of instructions to accomplish complex tasks.||RISC is provided with a reduced instruction set, which is typically primitive in nature.|
|7.Â Â Â||CISC processors are generally micro-coded, thereby allowing ROM-based CPU control. However, modern CISC processors also use hardwired units for easy CPU control.||RISC processors use hardwired units to control CPUs.|
|8.Â Â Â||A CISC processor works with 16 bits to 64 bits to execute each instruction.||A RISC processor utilizes 32 bits to execute each instruction.|
|9.Â Â Â||A CISC architecture uses one cache to store data as well as instructions. However, recent CISC designs employ split caches to divide data and instructions.||The RISC architecture relies on split caches, one for data and the other for instructions.|
|10.Â Â||CISC processors use a memory-to-memory framework to execute instructions such as ADD, LOAD, and even STORE.||RISC processors rely on a register-to-register mechanism to execute ADD, STORE, and independent LOAD instructions.|
|11.Â Â||The CISC architecture uses only one register set.||The RISC architecture utilizes multiple registers sets.|
|12. Â||Since CISC devices operate in a multi-clock environment, it supports addressing modes in the range of 12 to 24.||Since RISC machines operate on single clock cycles, it has limited addressing modes.|
|13.Â Â||CISC processors are capable of processing high-level programming language statements more efficiently, thanks to the support of complex addressing modes.||Since RISC processors support a limited set of addressing modes, complex instructions are synthesized through software codes.|
|14.Â Â||CISC does not support parallelism and pipelining. As such, CISC instructions are less pipelined.||RISC processors support instruction pipelining.|
|15.Â Â||CISC complexity is embedded in microprograms.||RISC complexity is pinned with compilers that execute the software program.|
|16.Â Â||CISC instructions require high execution time.||RISC instructions require less time for execution.|
|17.Â Â||CISC supports code expansion, which is similar to macro expansion, wherein a copy of inline functions is added in each place wherever it is called. Such inline functions run faster than normal functions.||RISC does not support code expansion.|
|18.Â Â||In the CISC architecture, the task of decoding instructions is quite complex.||In RISC processors, instruction decoding is simpler than in CISC.|
|19.Â Â||Some examples of CISC processors include Intel x86 CPUs, System/360, VAX, PDP-11, Motorola 68000 family, and AMD.||Examples of RISC processors include Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC.|
|20.Â Â||CISC processors are used for low-end applications such as home automation devices, security systems, etc.||RISC processors are suitable for high-end applications, including image and video processing, telecommunications, etc.|
RISC vs. CISC: Which is the better architecture?
Each processor architecture is powerful in its own way. As a result, both types are exploited for different applications, as revealed in the comparison table above.
If you look at the history of these processor types, you will realize that the CISC architecture was quite popular when microprocessors and microcontrollers were first introduced. This was due to the limited access to software capabilities at the time. However, as time went by, the software field matured, and with its growing sophistication, companies such as Apple invested in developing the RISC architecture.
However, today, the CISC architecture is almost obsolete as its development is becoming increasingly difficult. Since the technology was developed by Intel, the company continued to invest in it to keep its current hardware and software backward compatible with x86 processors.
Today’s advanced ARM devices, PICs microcontrollers, and intelligent devices such as smartphones use the RISC architecture since they are power-efficient, require fewer resources, and are faster. The only CISC devices existent today are Intel’s series of x86 processors.
The debate on which architecture is better has been around since the early 1980s. However, by studying both processors, one realizes there’s no definitive answer to the question. CISC is more hardware-centric, which implies that transistors on microchips may only multiply in years to come, thereby increasing the complexity on the hardware side. On the contrary, RISC presents a software-centric architecture that is easier to implement and modify. As a result, it can enter the market in much less time and continue to do so in the near future.
With each approach having its own share of benefits and drawbacks, it is difficult to weigh in on the better-architecture debate between CISC and RISC.
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