Google Uses AI to Design Next-Generation Chips in Just Six Hours

Google has been researching how artificial intelligence can be leveraged to design the next-generation of chips and processors for over a year now. The company last week released a paper detailing how they’ve used reinforcement learning-based ML models to develop their next AI Tensor Processing Unit.

Gordon MooreOpens a new window , the founder of Fairchild Semiconductor and Intel, in 1975 predicted that the number of transistors on an integrated circuit would double every two years. This observation, now known as Moore’s LawOpens a new window , has continued to hold true, but may very well be on the verge of being rendered obsolete.

As modern-day silicon is overhauled to accommodate the intricacies of running artificial intelligence (AI) models, Google has gone the other way and is now designing chips using AI. The company explained this cyclic clockwork, research for which has been going on for well over a year, in the science publication Nature.comOpens a new window last week.

Designing a chip, called floorplanning in technical circles, is an arduous months-long process that has so far remained one of the few areas that haven’t been receptive to automation. It seems that will change soon. “In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance, and chip area,” explained Google in a paperOpens a new window authored by 20 researchers.

Google itself isn’t a chip manufacturer per se but the Mountain View, CA-based company has developed several chips, and its Tensor Processing Unit (TPU) hardware specifically to support the processing of AI workloads for internal research. Google said it is already banking on the procedure to design its next iteration of TPUs for its AI-processing data centers, and possibly other commercial use cases.

Essentially, AI is being leveraged to help in the development of future-ready AI applications.

See Also: Realizing the Full Potential of Artificial Intelligence and Automation

Floorplanning

A Floorplan is the foundational and schematic representation of the placement of the major functional blocks of an integrated circuit. This includes memory subsystems, compute units, control logic systems, etc., which are in turn made up of transistors, diodes, resistors, capacitors, and the small metallic pathways that facilitate current and signal transmission, and connect all these components.

What makes a floorplan is the determination of the location, shape, and size of the components on a chip. Thus, it is basically the groundwork for figuring out the layout of the chip and to make out its area, wiring congestion, among other things.

According to EDNOpens a new window , Floorplanning includes “macro/block placement, design partitioning, pin placement, power planning, and power grid design. What makes the job more important is that the decisions which are taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.”

So, almost all aspects of the floorplan are based primarily on the specifications of the final product. This is why the design demands that every module is assigned an appropriate area and aspect ratio, every pin of the module is connected with the other modules, and that all modules are arranged in such a way that surface area is reduced.

But this is easier said than done owing to the complexities associated with designing modern-day chips. Initial chips from the early 1970s had between 1000 to 5000 transistors. The current ones have almost 50 billion transistors, which goes on to show what engineers are dealing with.

Engineers usually work with the help of computer-aided tools to figure out the optimal layout or the floorplan. Here, optimal not only refers to reducing the surface area but reducing it in such a way that performance or efficiency isn’t affected. In a centimeter-long chip, even a variation on the scale of micrometers can prove to throw the overall output and functioning into disarray.

“Chip floorplanning is analogous to a game with varying pieces (for example, netlist topologies, macro counts, macro sizes and aspect ratios), boards (varying canvas sizes and aspect ratios) and win conditions (relative importance of different evaluation metrics or different density and routing congestion constraints),” explained the paper co-led co-led by staff research scientists at Google Azalia MirhoseiniOpens a new window and Anna GoldieOpens a new window . “Even one instance of this game (placing a particular netlist onto a particular canvas) has an enormous state-action space.”

So How Can AI Help in Chip Design?

If you look at the floorplanning process, it resembles playing a computer game that involves piecing together multiple design elements.

Much like games, chips have a board, several movable components, and certain patterns that are more appropriate than others. Finding these patterns in a game can land players a win, and in the case of floorplanning, it can optimize the chip.

Google researchers used this analogy to transfer machine learning models used in games to the development of floorplans for chips, thus gamifying the design process.

Researchers added, “By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning.”

The reinforcement learning algorithm Google used to train the ML model is based on a dataset consisting of 10,000 chip floorplans. Every single floorplan from the dataset, some of which were randomly generated, is labeled with a reward depending on the wirelength, density, placements, etc.

“As our agent is exposed to a greater volume and variety of chips, it becomes both faster and better at generating optimized placements for new chip blocks, bringing us closer to a future in which chip designers are assisted by artificial agents with vast chip placement experience.”

Researchers did face a hurdle with mapping the IC board for chip floorplanning, which is more complex than a board game. For example, the popular game Go has a state-space of 10360. Compared to that, the state-space of placing 1,000 clusters of nodes on a grid with 1,000 cells is enormous, and is of the order of 1,000! (greater than 102,500).

To overcome this, researchers developed a neural network capable of predicting the rewards for various component placement and netlists. As a result, AI successfully determined the good placements from those that can be bad.

See Also: How to Measure the ROI for Artificial Intelligence

How Well Does AI Work in Designing Chips and Can It Help in Alleviating the Global Chip Shortage?

Google managed to design floorplans for chips that should be at par with or better than the existing ones designed by humans.

Excited to share that our work has been published in Nature! Our RL agent generates chip layouts in just a few hours, whereas human experts can take months. These superhuman AI-generated layouts were used in Google’s latest AI accelerator (TPU-v5)!

— Anna D Goldie (@annadgoldie) June 9, 2021Opens a new window

The image above is purposefully blurred to protect the design’s confidentiality, however, the differences in the design are visually evident and quite prominent.

The white and the green areas, which represent macros and standard cells respectively, are neatly stacked by human efforts. AI on the other hand made concessions on the looks and went with the rewards-driven approach, as it was taught.

Let us remind you once again that this chip was designed in just six hours as opposed to several weeks, and is still performing equally well as the human ones. The biggest advantage of this technique is that it can help save hundreds, maybe thousands of hours of design efforts by engineers.

The applicability of Google’s research for chip fabrication is non-existent, which is why there is little reason to believe that it can be used to relieve choked supply lines due to the global chip shortage. However, the technique could prove to be beneficial for chip manufacturers seeking to further expand their line of offerings and shed legacy products until the shortage is resolved.

For instance, Intel is still stuck on its 7 nm process chip while its competitors have moved on to the 5 nm, and in the case of IBM to a 2 nm chip.

Wrapping Up

Google’s breakthrough is expected to further accelerate the already high pace of innovation when it comes to semiconductors. It is the kind of a breakthrough that compliments what we already know about chips as well as AI, which can then be used to keep on enhancing both.

The technique is already used in Google’s latest AI accelerator TPU-v5, while the code used to replicate Google’s findings is available from the corresponding authors “upon reasonable request”.

Amin VahdatOpens a new window , Google fellow and vice president of systems infrastructure earlier this year in March hinted at the in-house development of computing hardware by the company. He wrote in a blog postOpens a new window , “Compute at Google is at an important inflection point. To date, the motherboard has been our integration point, where we compose CPUs, networking, storage devices, custom accelerators, memory, all from different vendors, into an optimized system.”

“But that’s no longer sufficient: to gain higher performance and to use less power, our workloads demand even deeper integration into the underlying hardware. Instead of integrating components on a motherboard where they are separated by inches of wires, we are turning to ‘Systems on Chip’ (SoC) designs where multiple functions sit on the same chip, or on multiple chips inside one package. In other words, the SoC is the new motherboard.”

It remains unclear whether Google, which already competes with other tech giants in cloud computing, computer software, web search, computer hardware, AI, and advertising, is looking to go toe to toe with Arm, Intel, TSMC, etc., in the semiconductor space in the future. The possibility, however, cannot be ruled out.

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