Semiconductor industry heavyweights are teaming up to standardize the use of chiplets in chip designing. The likes of TSMC, Samsung, Intel, AMD, Qualcomm, Advanced Semiconductor Engineering (ASE), and others have formed a coalition to launch the Universal Chiplet Interconnect Express (UCIe) technology and to bring it to mainstream use.
Moore’s law, i.e., the hypothesis that the number of transistors on a single, monolithic dense chip will double every two years, is almost obsolete. Stated by Gordon Moore, the co-founder of Fairchild Semiconductor Lab and Intel, it held true for over five decades, but as process nodes became advanced, chip designers realized Moore’s Law would have to be put to rest.
The law didn’t actually dictate chip designs but pointed the direction in which the semiconductor industry was heading, i.e., the use of smaller transistors. Decades of exponential growth have shrunk the transistor to the scale of a few nanometers. Enter chiplets, which are nothing but the building blocks of advanced chips.
The use of chiplets has consistently increased over the years, thanks to chip design limitations, particularly concerning the size of the chips. Known as reticle limit, it forces chipmakers to design and fabricate chips on a limited chip surface area. But as chip designs evolved, the reticle limit increased. The solution for designs that exceeded the reticle limit was to divide the chips into smaller units.
These smaller units, which in turn are made up of dies, are known as chiplets. They are tiny integrated circuits clubbed with other chiplets to form a whole chip. Each chiplet has a specific function and works in tandem with others to deliver the desired output.
The necessity of a chiplet-based chip design became apparent during the 16 nm node era. Design and manufacturing costs soared significantly while the cadence of evolution to the next-generation chip increased.
 Design Cost Across Different Process Nodes | Source: IBS, UCIe ConsortiumOpens a new window
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Chiplets proved to be particularly helpful in this regard. The use of chiplets requires advanced manufacturing tech such as electronic design automation (EDA), die-to-die interconnect, etc. Only some in the industry have all the right tools. Those who did implement them, and over time, as the use of chiplets increased, the industry realized incorporating a chiplet-based design for a semiconductor is not only a technological necessity but also quite economical.
That is not to say that the existing ubiquitous monolithic designs are being discarded. Not all computing requires advanced nodes, so monolithic or single wafer chip design will continue to power a significant chunk of devices. Nevertheless, it is safe to say that once chiplet-based designs of semiconductors become mainstream, the devices in which they are used will follow suit and leave behind outdated hardware.
Besides EDA and die-to-die interconnect technology, the lack of standards and an industry-wide ecosystem hindered the adoption of chiplets. In short, UCIe is the industry’s effort to keep up the rapid evolution of semiconductors, with which we have become accustomed over the previous half-century.
TSMC (54%) and Samsung (17%) contribute over two-thirdsOpens a new window of the global chip manufacturing and have the most advanced foundries (Intel is playing catch up). Intel and AMD are premier American chipmakers, with the former having charted an ambitious roadmap. Qualcomm’s presence in the mobile chip space is next only to MediaTek. Arm, a company whose IP is leveraged by almost all global chipmakers, is also a part of the consortium.
Additionally, Google Cloud, Meta, Microsoft Corporation are also joining hands with the stated semiconductor players. This is probably because two of the three companies have extensive cloud and hyperscale businesses (nearly one thirdOpens a new window of global market share). At the same time, all three cater to end-users through consumer products, which require general-purpose CPUs.
Remarkably, NVIDIA (the biggest GPU maker with over 80% market shareOpens a new window ), AWS (biggest cloud vendor with nearly 33% share), IBM, GlobalFoundries, and United Microelectronics Corporation (UMC) haven’t joined the consortium yet.
UCIe is modeled explicitly after PCIe (peripheral component interconnect express), an industry interface standard for high-speed serial computer expansion. It is used to implement computer designs that facilitate high-speed, low latency connection to peripheral devices such as external GPUs, storage devices (SSD, HDD), Wi-Fi cards, etc.
UCIe 1.0 thus incorporates a software stack derived from PCIe that dictates die-to-die I/O physical layer and die-to-die protocols. In simple words, it will enable manufacturers to connect multiple chiplets using one single method. This will also help designers connect chiplets designed with different IPs, designs, packaging technologies, by multiple vendors, thereby offering greater flexibility and design options.
“The opportunity to mix-and-match different ‘building block’ chiplets allows customized solutions to be quickly developed for different usage models,†explained Parthasarathy Ranganathan, VP/technical fellow at Google.
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Open Chiplet Ecosystem | Source: UCIe Consortium
“Additionally, different IP blocks can be manufactured in different process technologies best suited for the function: for example, input/output (I/O) blocks can be manufactured in older process technologies while performance-sensitive compute blocks can be built on the latest technology generation. Such heterogeneous technology matching can avoid the long delays associated with migrating the full IP portfolio to the leading technology node.â€
UCIe 1.0 is already ratified by the consortium, which is open for expansion and membership. The consortium is already eyeing the development of the next generation of UCIe tech to define the chiplet form factor, security, protocol stacks, and management.
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